The present invention relates to input/output controllers for use in digital data processing systems for transferring data between a memory and one or more peripheral devices, and more particularly relates to a direct memory access (DMA) controller which reads data into a register and writes data out of that register in the same cycle.
Direct memory access controllers which transfer data between peripheral devices and a main memory by accessing the memory directly are well known. Since the input/output speed of the peripheral devices is generally different than the input/output speed of the memory, controllers which allow for the transfer of data between the memory and a peripheral device without tying up the data processing system for long periods of time are used.
U.S. Pat. No. 4,371,932 issued Feb. 1, 1983 to Dinwiddie Jr. et al. for "I/O Controller For Transferring Data Between A Host Processor And Multiple I/O Units" discloses an I/O controller which includes an interleaving mechanism for enabling concurrent performance of two different modes of data transfer between a host processor and the I/O controller.
U.S. Pat. No. 4,075,691 issued Feb. 21, 1978 to Davis et al. for "Communication Control Unit" discloses a communication control unit for operably coupling a plurality of peripheral devices to a data processing system including a direct memory access module for communicating with a memory of the data processing system.
Other patents which show the state of the art include: U.S. Pat. No. 3,818,461 issued June 18, 1974 to Ward et al. for "Buffer Memory System"; U.S. Pat. No. 4,040,027 issued Aug. 2, 1977 to van Es et al. for "Digital Data Transfer System Having Delayed Information Readout From A First Memory Into A Second Memory"; U.S. Pat. No. 263,648 issued Apr. 21, 1981 to Stafford et al. for "Split System Bus For Direct Memory Access of Peripherals In A Cathode Ray Tube Display System"; and U.S. Pat. No. 4,371,929 issued Feb. 1, 1983 to Brann et al. for "Multiprocessor System With High Density Memory Set Architecture Including Partitionable Cache Store Interface To Shared Disk Drive Memory."